Recessed dielectric isolation and, in particular, recessed silicon dioxide isolation are known in the large scale integrated semiconductor art for providing electrically isolated pockets on the same silicon chip, for separating base and collector contact regions of transistors constructed within isolated pockets, and for insulating conductors from the underlying silicon substrate. It is also known that recessed dielectric isolation can be produced by first selectively removing silicon from a substrate so as to form trenches in the substrate and then filling the trenches with dielectric material such as, for example, in the manner described in U.S. Pat. No. 3,966,577, issued on June 29, 1976 to Arthur K. Hochberg for Dielectrically Isolated Semiconductor Devices. This prior art teaches a structure but does not detail the process limitations or conditions to achieve that structure except in general terms.
In the interest of minimizing the silicon chip area occupied by the dielectrically filled trenches, sputter etching processes and reactive ion etching processes have been utilized to form the trenches in the silicon substrate. A reactive ion etching process is described in copending application Ser. No. 594,418, filed July 9, 1975, now abandoned, in the names of J. M. Harvilchuck et al for "Reactive Ion Etching of Silicon" and assigned to the present assignee, to provide trenches having vertical sidewalls without significant mask undercutting and the tapered walls which are characteristic of chemical etching processes.
In another copending application, Ser. No. 824,361, filed Aug. 15, 1977, now U.S. Pat. No. 4,104,086, for "Method For Forming Isolated Regions Of Silicon", in the names of the present inventors and assigned to the present assignee, a method for achieving well filled deep narrow grooves with near vertical walls is described. The method consists of the formation of slightly tapered narrow grooves cut through burried highly doped Si regions, thermal oxidation of said grooves and proper filling in of remaining grooves with a vapor deposited dielectric material. The application points out the need for forming slightly tapered walls and discusses the dependency of the quality and planarity of the dielectric filling material on the groove taper angle and groove width, respectively. The method also consists of a back etching of the filling material, which covers the total wafer, with reactive ion etching to remove the material everywhere from the surface to leave only the isolation pockets.
There remains a need, however, for a simplified process for simultaneously forming narrow deeply recessed dielectrically filled trenches of different depths for separating base and collector contact regions and for separating device areas of integrated transistor devices as well as for producing wide deeply recessed dielectrically filled trenches for isolating surface conductors from underlying silicon substrates. It is also desirable that these objectives be achievable by a single compatible series of process steps.